In the following article, I expect to explain the basics of computer architecture using the two very famous computer models: the Von Neumann model and the Harvard model. If you are new to computer architecture, the following article will help you to get a clear understanding of the major difference between Von Neumann and Harvard Architecture models.
Von Neumann Architecture
The Von Neumann computer architecture was designed and developed by the great mathematician Joh Von Neumann around the 1940s.
Von Neumann architecture explains a model for a stored-program digital computer. It consists of a single processing unit and single separate storage to hold both instructions and data. Keeping program data and instruction data in the same memory unit is referred to as a “stored program concept”
A PC that stores data and programmed instructions to read-write in RAM is built on Von Neumann Architecture.
The components of a computer built on Von Neumann Architecture include:
- Input — an input signal comes from an input device such as a keyboard etc.
- Output — and output signal generated after processing a command from CPU. They are output by devices such as to monitor etc.
- Central Processing Unit — holds ALU (Arithmetic Logic Unit), CU (Control unit), and registers.
- Control unit — controls the operations of ALU, memory unit, Input/Output.
- ALU — perform arithmetic operations such as addition and substation.
- Memory Unit — it is partitioned and contains an address with its content. It stores commands
- Registers — the tiny block in CPU made up of high-speed memory cells which store data to be processed, and perform all logical, arithmetic, and shift operations.
- Buses — the parallel wire sets which connect two or more components inside the CPU.
The Basic Process of a computer built in Von Neumann Architecture
- The input comes in and is stored in the memory (RAM).
- The input becomes the command and ready to be processed.
- The CU in the CPU fetches the command from the memory and checks which operations to be performed.
- The fetched command is processed by CU and ALU in the CPU.
- After processing completes, the control unit stores the result in memory again.
- Finally, the output is displayed via an output device.
Over the years, the computer processing power and memory capacity increased, but the transfer speed of memory was not sufficient resulting in the “Von Neumann Bottleneck”. This occurs due to spending a great deal of time by CPU in an idle state while waiting to fetch data from the memory. Hence, how fast the processor is, performance is depending on the data transfer rate between memory and processor.
To overcome the bottleneck issue, some modifications were added to Von Neumann Architecture as follows,
d) New types of RAMs
f) PIM (Processing in Memory)
Both Harvard architecture and Von Neumann Architecture consists of the same components. Nevertheless, in contrast, the instruction fetch, and data transfer can be performed simultaneously in Harvard architecture. This is because the computers developed under Harvard architecture consists of two buses for instruction fetch and data transfer, separately. The instructions and data are kept in separate memories and transferred through separate buses.
In Harvard architecture, since data and instructions are passed in different busses, the possibility to occur data corruption is minimum.
Hence, the computers built on this architecture result in high performance.
Not only that, due to having separate memory for instructions and data, greater memory bandwidth is possible in Harvard computer models.
Due to having separate buses and memory, this architecture is complex thus costlier than the von Neumann model.
Since the pure Harvard architecture suffers from complexity and cost issues, under some improvements, ‘Modified Harvard Architecture’ was designed. The was to lose some strict separation between instructions and data while still ensuring the higher performance.
The 03 main modifications applied to build Modified Harvard Architecture are:
- Split-cache architecture.
- Instruction-memory-as-data architecture.
- Data-memory-as-instruction architecture.
Comparison of Von Neumann and Harvard Architecture
Non — Von Neumann Models
- Most computers read one instruction at a time and execute it and they can be classified under Von-Neumann architecture. And all of them have the weakness Von Neumann bottleneck.
- Term non-Von-Neumann is generally used to identify computers that explicit a radical change and improvement from standard Von Neumann architecture.
- Unlike Von — Neumann architecture, they do not resemble the concept of sequential flow of control and concept of variable. There are immutable bindings in-between names and constant values, instead of variables.
- Non-Von Neumann models can possess a high degree of parallelism (multiple computations are performed at the same time running the programs faster.)
- Dataflow architecture. Ex: NON-VON supercomputer (It is a non-Von-Neumann supercomputer that utilizes parallelism in a great deal.)
- Reduction architecture
- Quantum computing
- Neural Networks
- MIMD architecture — The machines with this architecture possess a number of independently operating processors that function asynchronously.
- DNA computing — Instead of common Si-based chips, computing is performed using a technology developed with DNA, biochemistry, and molecular biology-based hardware.
- Parallel computing — high-performance computer systems that are equipped with multiple processors.